Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.

The FICS Research Institute (University of Florida) has published a new research paper titled “Secure Physical Design.” This is the first and most comprehensive research work done in this area that ...

Today 's problems in chip design are related to flow, not tools.Building an in-house flow — the successful interplay of tools, data and people — has become increasingly difficult because there aren't ...

As semiconductor technology pushes the boundaries of scale and complexity, traditional VLSI physical design methodologies are struggling to keep pace. The rise of Artificial Intelligence (AI), ...

Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and ...

IROC Technologies was tasked by the European Space Agency (ESA) to assess the suitability of Ultra Deep Submicron (UDSM) technology nodes below 22 nm for space applications. IROC set out to build a ...

Nearly all designs at advanced process nodes need some sort of power-saving strategy. As more designs employ advanced low-power techniques, design teams are discovering huge implementation hurdles ...