Consider a 64-bit microprocessor, with a 32-bit external data bus, driven by a 10-GHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals six input clock cycles. What is the maximum data transfer rate across the bus that this microprocessor can sustain, in bytes/sec? To increase its performance, would it be better to make its external data bus 64 bits or to double the external clock frequency supplies to the microprocessor? State any other assumptions you m

Problem 3 Solution Video | Principles of Microeconomics | Economics | MIT OpenCourseWare